Low-power single-precision IEEE Floating-point unit
Sheetal A. Jain · 2003
Floating point adders are area and power intensive, but essential in high performance systems. The Software-Controlled Architectures and Low Energy (SCALE) project requires a low-power single-precision IEEE floating-point adder cluster. Two adder architectures, one containing a single longer computational path, and one containing two shorter parallel computational paths were implemented using minimal area modules. Inputs to the parallel computational paths were registered, and only enabled when that computational path was valid, reducing switching activity. Energy measurements were made of the dual path adder with and without inhibit control and the single path adder, to determine the most energy efficient design.