Complex Multiplier Suited for FPGA Structure
Keiichi Satoh, Jubee Tada, Yasutaka Tamura, Gensuke Goto · Journal of Communication and Computer · 2009
In this paper, the author propose high- performance complex multipliers suited for Field-Programmable-Gate-Array (FPGA). The proposed complex multipliers are designed by effectively utilizing LUT (Look-Up-Table) and carry-chain which are basic components in FPGA. To design the circuits, the author utilize Radix-4 Booth algorithm for partial product generation and Wallace tree utilizing effectively LUTs and carry-chains for the partial product compression. The author estimated path delay and scale of the proposed complex multipliers by utilizing synthesis tool, and showed shorter path delay and smaller scale than circuits synthesized by VHDL operator ('*', '+', and '-').