A methodology for integrating design and test at the system level
Shu-Kau Chiu · OhioLink ETD Center (Ohio Library and Information Network) · 1992
Recent progress of high level synthesis has illuminated an effective aid for system designers. However, to produce a high quality design, there is a need to consider design for testability (DFT) during the synthesis process. Motivated by this requirement, a methodology is presented in this thesis to cover the gap between design and test at the system level. Following this methodology, two approaches--heuristic and integer linear programming--are given to analyze the testability for large or small systems, respectively. Applying to a Built-In Self-Testing technique, the heuristic approach is shown to be fast and effective on benchmark circuits. Demonstrated with an application to the Symbolic Test Pattern Generation Technique, the integer programming approach is promising for reasonable-sized circuits. Incorporation of the heuristic approach into an experimental high level synthesis system, SYNTEST, has been completed with the overall objective of generating testable designs at the register transfer level.