Abstraction Techniques for Diagrams of RTL and System Level Designs
Eunchoul Lee, Kyosun Kim, Seok-Hee Jeon, Gun-Ho Ok, Sung-Hwan Oh · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2005
ion Techniques for Diagrams of RTL and System Level Designs Eunchoul Lee, Kyosun Kim, Seok-Hee Jeon, Gun-Ho Ok, and Sung-Hwan Oh 1 Department of Electronic Engineering, University of Incheon 2 Entasys Design, Inc. [email protected] Abstract – The automatic generation of circuit diagrams has been practically used in the HDL based design for decades. Unfortunately, the diagrams in the RTL and system level have become too complicated for the designers to identify signal flows. In this paper, we propose two techniques to enhance the readability of the complicated higher level diagrams. They include i) the transformation of repetitive instances and terminals into vector forms, and ii) a flat tap which simplifies the two level bus ripping structure that is required for the connection of a bundle net to multiple buses. Towards validating the proposed techniques, the diagrams of an industrial strength design example are generated. The complexity of the diagrams has been reduced by up to 90% in terms of the number of wires, the aggregate wire length, and the area.