Flexible Multi-IP Verification Methodology Based on an FPGA Platform
Jin Woo Song, Ki‐Seok Chung · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in an SoC design increases, verifying multiple IPs together is really important to reduce time-to-market. In this paper, we propose a novel FPGA platform based verification methodology which tests multiple IPs together using a single testbench. We’ve found that commercially available FPGA platforms such as Altera Cyclone, Xilinx Spartan provide excellent environment in verifying the functionalities of mutually interactive multiple IPs. In our methodology, an FPGA device is used mainly for verification purposes. We program the soft core CPU, the bus architecture and other peripherals into the FPGA, which will execute C-based testbench and mutually interactive IPs are also programmed into the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator which will automatically connect the bus architecture and the IP module together. Using this platform, we have verified up to 5 IPs together successfully, but we can verify more IPs together easily. Time and effort to verify complex IPs have been significantly reduced using this methodology.