A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set
MohammadReza Taheri, Nasim Shafiee, Mohammad Esmaeildoust, Zhale Amirjamshidi, Reza Sabbaghi‐Nadooshan, Keivan Navi · 2016
The moduli set 2 n−1 − 1, 2 n+1 − 1, 2 n , 2 n − 1 has been recently proposed in literature for class of 4n-bit dynamic range in residue number system. Due to only utilizing modulus in the form of 2 k − 1 besides modulo 2 n , this moduli set enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only does the efficiency of a RNS system depend on the residue arithmetic unit but it also is limited to the residue to binary converter. In this paper, a new two level residue-to-binary converter architecture based on Mixed Radix Conversion (MRC) is presented for the aforementioned moduli set. The proposed converter includes two levels of design based on MRC properties. Firstly, the 3-moduli subset 2 n−1 − 1, 2 n+1 − 1, 2 n − 1 is properly organized and as it does not calculate several values, it results in some cost modifications. Eventually, a two-moduli set 2 n−1 − 1 2 n+1 − 1 (2 n − 1) , 2 n is formed to compute the binary of RNS counterpart. The proposed architecture is shown to be more efficient both in terms of hardware cost and conversion delay in comparison with the related state-of-the-art works.