AN OPTIMIZED ALGORITHM FOR SIMULTANEOUS ROUTING AND BUFFER INSERTION IN MULTI-TERMINAL NETS
Nasir Shaikh Husin, Chessda Uttraphan · ARPN Journal of Engineering and Applied Sciences · 2015
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As design dimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is proven to be an effective technique to minimize the interconnect delay. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their area. Many conventional buffer insertion algorithms do not consider these obstacles. This paper presents an algorithm for simultaneous routing and buffer insertion using look-ahead optimization technique. Simulation results show that the proposed algorithm can produce up to 47% better solution compared to the conventional algorithms. Although research has shown that simultaneous routing and buffer insertion is NP-complete, however, with the aid of look-ahead technique, the runtime of the algorithm can be reduced significantly.