Novel Memory Controllers for Latency Reduction of Dual-port SDRAM
Ho Lim, Hyosuk Kwak, Jong‐Wha Chong · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
In this paper, a semaphore authority management (SAM) controller which minimizes semaphore latency of dual-port SDRAM (DPSDRAM) is proposed. A shared bank in the DPSDRAM includes a semaphore which prevents access conflict between two ports. However, the latency caused by the semaphore reduces the speed of data communication between two processors. The SAM algorithm is used to minimize the latency. A register, which is synchronized with the semaphore register in the shared bank, is designed in the SAM controller for preventing the latency of reading semaphore register. The methods of semaphore authority prefetching and automatic semaphore release are added in the SAM controller for reducing the additional latency caused by the semaphore. The results of experiments using DPSDRAM with SAM controllers at 66Mhz show that data transfer rate between two processors is enhanced by 60% compared with the conventional controllers.