Application specific logic-in-memory
Larry Pileggi, Qiuling Zhu · 2013
This thesis aims to exploit recent cutting-edge low level technology advances to build energy-efficient computing platforms to accelerate today's memory-bound computing that is difficult to optimize on traditional computing systems. Specifically, we proposed a methodology for efficiently constructing application-specific logic-enhanced smart memory (namely, logic-in-memory or LiM) hardware substrates, on which we can efficiently implement specific data-intensive functions by co-optimizing the algorithm and hardware. The proposed LiM hardware substrate incorporates customized logic functions, or intelligence, into a standard memory abstraction. It enables localized computation by blurring the memory and processing boundaries, thereby minimizing unnecessary data transfer and overhead to save energy. Moreover, LiM designs are customized to a single or narrow-class of functions by stripping out the flexibility and generality that are the major causes of computing inefficiencies. Eventually, the proposed LiM computing platform reaps the benefits of both logic-memory integration and special-purpose hardware acceleration, and it can optimize the system to a level that is impossible with general purpose computing or configurable hardware computing. The ability to effectively and affordably model, design and synthesize application-specific LiM computing devices is enabled by two recent technology advances. The first is the regular pattern construct-based IC design that facilitates the co-design and co-synthesis of logic and embedded memories [1]. This allows logic and memory cells to be tightly integrated at a much finer granularity, giving rise to logic-in-embedded memory designs (i.e., on-chip LiM). The second is the emergence of 3D integration technology that makes it possible to bring the on-chip LiM closer to the external memory (e.g., DRAM). For example, we can stack the on-chip LiM on top of 3D die-stacked DRAM dies (i.e., 3D-stacked LiM), and exploit through silicon vias (TSVs) for vertical inter-die connection. 3D-stacked LiM combines the on-chip LiM processing capabilities, with the huge storage capacity and high memory bandwidth offered by 3D die-stacked DRAM, to provide new opportunities to accelerate the memory-bound problems in an efficient way. Importantly, an LiM-based design methodology is effective only if the application algorithms and hardware structures are co-optimized to match each other. Therefore, another important direction of this thesis is to map appropriate computation workloads of a memory bound application to the underlying LiM hardware. We achieved this by either adapting the algorithm and memory access patterns to match the hardware LiM capabilities, or by designing effective memory circuits and architectures to match the algorithm characteristics. To make such application-specific hardware customization affordable, we have developed an end-to-end LiM design automation framework that can efficiently and reliably synthesize the LiM hard IPs directly from system level specifications. This design automation framework also facilitates the design space exploration and system co-optimization. For the purpose of demonstration, this thesis provides end-to-end case studies for both of the on-chip LiM designs and 3D-stacked LiM designs. More specifically, we map a synthetic aperture radar image reformatting algorithm to a localized interpolation based on-chip LiM design. We also map a sparse matrix-sparse matrix multiplication kernel to a model of a dedicated 3D-stacked LiM computing platform to accelerate large-scale sparse graph problems. We co-optimize the algorithm formulations, data storage formats, memory hierarchy, as well as the underlying hardware circuits, to produce completely balanced systems that can achieve superior high computing performance at extremely low cost.