A Power-of-Two Variable Length DFT Processor Design for Communication Systems
Hun‐Chen Chen, Jui-Cheng Yen, Kuo-Tai Fan, Chien‐Wan Hun · 2008
This paper presents a power-of-two variable length discrete Fourier transform (DFT) design using the low hardware cost distributed arithmetic (DA) approach for communication systems. The length of proposed DFT can be varied up to 4096. For algorithm factorization of the proposed DFT with long length, instead of commonly used in FFT, we first decompose the length of DFT into 2-D short length DFT by Cooley-turkey algorithm and reform the short one as cyclic convolution, and then further factorize the cyclic convolution with short length cyclic convolutions by using the pseudocirculant factorization algorithm. Regarding the hardware design, combining with the techniques of architecture folding and memory content sharing in DA architecture, a hardware efficient variable-length DFT processor is designed as well as realized for the communication systems. Compared with the existing variable-length FFT design, in additional to the feature of short latency, the proposed design can be an alternative of DFT design with competitive hardware cost under the same throughput rate.