Hybrid message passing and threading for heterogeneous use on CPUs and the Intel® many integrated core architecture
Vincent C. Betro, R. Glenn Brook, Ryan C. Hulguin · 2012
To explore the potential impact of the Intel® Many Integrated Core (Intel® MIC) architecture and related programming models on the supercomputing community, several applications are ported to and subsequently studied on a 50-plus-core Intel® Xeon Phi™ coprocessor deployed at the National Institute for Computational Sciences (NICS). One of the studied applications -- a 2D Boltzmann-BGK solver -- employs the native execution model, in which the Intel Xeon Phi acts as a standalone compute node on which parallel code is executed directly via MPI or interactive login. Another application -- a Poisson solver -- employs both the native and offload execution models, the latter of which migrates computational kernels or sections of code that are flagged by special pragmas to the Intel Xeon Phi for execution while the primary code runs on the Intel® Xeon® processor. A final application -- a trapezoidal rule integration scheme -- is instrumented to run on the Intel Xeon Phi and the Intel Xeon processor simultaneously, and the results of different levels of heterogeneity in execution are studied. Information regarding the porting and scalability of each application code is presented.