Design and Evaluation of a Coarse-Grained Reconfigurable Architecture
Yoonjin Kim, Chul‐Soo Park, Shin-Won Kang, Hyunjik Song, Jin‐Young Jung, Ki‐Young Choi · 대한전자공학회 ISOCC · 2004
Coarse-grained reconfigurable architectures have become more attractive with the increasing requirement of more flexibility and higher performance in embedded systems design. In this paper, we suggest a design space exploration flow that enables effective optimization of reconfigurable architectures through SystemC Modeling. In the suggested flow, application-to-architecture mapping process tries loop pipelining technique to find a better performance. According to the result of design space exploration, we implement a coarse-grained reconfigurable architecture in RT level. For the evaluation, we take H.263 encoder as the application. Estimated results show significant improvement over previous approaches.