16-Channel Three-Parallel Reed-Solomon Based FEC Architecture for 100Gb/s Optical Communications
Jeong-In Park, Chang-Seok Choi, Hanho Lee · ICEIC : International Conference on Electronics, Informations and Communications · 2010
This paper presents a high-speed, low-complexity Forward Error Correction (FEC) architecture based on a time-multiplexing three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. We have designed a high-speed three-parallel RS(255,239) decoder. The derived structure can also be applied to implement the 100-Gb/s RS decoder architecture. We implemented the 100-Gb/s RS-based FEC (RS-FEC) with 90-㎚ CMOS standard cell technology in a supply voltage of 1.1V. The implementation results show that 16-channel three-parallel RS-FEC architecture can operate at a clock frequency of 625㎒ and has a throughput of 240-Gb/s for 90-㎚ CMOS technology.