TEMPO - a Tool for Automatic Verification of Asynchronous VLSl Systems
MA Jabri, Wai Lun Mang · 1989
This paper presents TEMPO, a CAD environment for reasoning about asynchronous VLSI systems. TEMPO is being developed using Brel, a knowledge-based system shell (described in a companion paper), and is based upon temporal logic concepts. The system is aimed at assisting VLSI designers in the manipulation of asynchronous circuits. It uses temporal logic as a circuit hardware description language and provides, therefore, a powerful tool for formal verification.