A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints
Koji Inoue, 弘士 井上, Kazuaki J. Murakami, 和彰 村上, コウジ イノウエ, Kazuaki J. Murakami · Institutional Repositories DataBase (IRDB) · 2001
On-chip caches have been playing an important role in achieving high performance processors. In particu-lar, much higher performance is required for instruction caches because one or more instructions have to be is-sued on every clock cycle. In other words, from energy point of view, the instruction cache consumes a lot of energy. Therefore, it is strongly required to reduce the energy consumption for instruction-cache accesses. In direct-mapped instruction caches, tag comparison and data read are performed in parallel. Thus, the total energy consumed for a cache access has two factors: the energy for the tag comparison and that for the data read. Cache subbanking is one of approaches to reduc-ing the data-access energy: the data-memory array is partitioned into several subbanks, and only the sub-bank which includes the desired data is activated [1]. We have calculated the energy consumption for a 16 KB direct-mapped cache based on Kamble’s model [1]. Note that the energy for I/O drivers and address de-coder is not included in this calculation. As a result, it has been observed that increasing the number of sub-banks reduces a lot of energy for the data memory. Since the tag-access energy is maintained, however, the effect of the tag comparison becomes a significant fac-tor on the total energy consumption. In fact, where the subbank width is the same as the processor-word width, the energy consumed for the tag-memory ac-cesses occupies about 30 % and almost half of total en-ergy in 32-bit and 64-bit microprocessors, respectively. 2