A digital filter optimization method for low power digital wireless communication system
Kousuke Tarumi, Taizo Tsujimoto, Hiroto Yasuura · Kyushu University Institutional Repository (QIR) (Kyushu University) · 2003
In this paper, we introduce a design method for a low power digital baseband processing circuit. In particular, we focus on a digital FIR(Finite Impulse Response) filter that is a part of the digital baseband processing. Because the digital filter contains large power consuming components, such as adders and multipliers. We propose a design method to reduce power consumption of the digital FIR filter circuit by optimizing bitwidth of inputs of the mutipliers and the adders. We found that the power consumption and the circuit area of digital FIR filter circuit designed by our approach are about 82.8 % reduction and 67.3 % reduction compared with the digital filter whose coefficient is designed in 16-bit. 1.