CONSTRUCTING CHECKERS FROM PSL PROPERTIES
Radu Gheorghe Grigore · International Conference on Control Systems and Computer Science · 2005
Model checking and simulation are the main techniques widely used in hardware verification. The past years trend is to bring together these two verification techniques in order to employ knowledge and tools produced by one to help the other. This paper describes a tool that translates properties written in PSL, a model checking language, into checkers written in languages suitable for simulation. The tool has two main focuses: first, retargetability, and second, simplicity, efficiency and clarity of the resulted checkers. However, its speed is in the same order of magnitude with those of commercial tools already existing on the market.