Fast Fault Coverage Estimation at the Transistor Level
PC Maxwell · 1987
One of the most time consuming activities in the design of VLSI systems is the determination of fault coverage for a given test set. This information is crucial in the generation of test patterns, in order to ensure a system is adequately exercised. Fault simulation may be employed to determine fault coverage, but the time required to perform this rises, at best, as the square of the number of gates/devices. Efforts have been directed at reducing the computation time required for full fault simulation, including the use of testability analysis programs, and statistical fault estimation. This paper is concerned with the latter, in particular, the estimation of fault coverage from the results of fault-free simulation. Existing approaches carry out this analysis from the gate level without considering how the gates are constructed. After reviewing gate level approaches, this paper considers transistor level descriptions and it is shown how some structures (notably those involving pass transistors) cannot be modelled satisfactorily at the gate level, and require special methods to arrive at controllability and observability metrics for circuit nodes. Expressions are developed for the estimation of controllability, observability and fault detection probabilities for both switch logic and active gate structures, based on simple counting operations carried out during fault-free simulation. It is shown how an existing switch level simulator is very easily modified to allow rapid fault information to be obtained.