HighPerformance Arithmetic Units
2009
This chapter contains sections titled: Some Optimal Schemes for ALU Implementation in VLSI Technology A 4.5 NS 96B CMOS Adder Design Improved CLA Scheme with Optimized Delay High-Speed Binary Adder A Sub-Nanosecond O.5 ?>m 64b Adder Design A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis SPIM: A Pipelined 64 ?????? 64-bit Iterative Multiplier A 54 ?????? 54-b Regularly Structured Tree Multiplier A 4.4 ns CMOS 54 ?????? 54-b Multiplier Using Pass-Transistor Multiplexer A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach A 4.1-ns Compact 54 ?????? 54-b Multiplier Utilizing Sign-Select Booth Encoders Division and Square Root: Choosing the Right Implementation 167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages Radix-4 Square Root Without Initial PLA 167 MHz Radix-4 Floating Point Multiplier