Cotransformation for the logarithmic number system with application to model predictive control
Mark G. Arnold, Mayuresh V. Kothare, Panagiotis D. Vouzis · 2008
The proliferation of embedded systems is mainly attributed to the increasing integration of functionalities into increasingly cheaper hardware, which is developed by considering factors such as occupied area, power consumption, and performance. When strict specifications have to be met with respect to the aforementioned parameters, different implementation options have to be explored. In this context the Logarithmic Number System (LNS) can be considered as the hardware arithmetic system for the arithmetic operations of an embedded application. The research conducted in LNS is focused, to great extent, on the optimization of the addition and subtraction operations, and in this work a subtraction method called co-transformation is studied. A subtle error in an existing cotransformation technique is clarified and corrected, and novel cotransformations are presented. Additionally, algebraic formulas are derived that calculate analytically the memory requirements of the cotransformation implementations facilitating the exploration of the design space. The novel techniques are compared with existing ones and it is shown how they improve the area and the accuracy, but decrease the speed of a circuit. Similarly, a technique that can reduce the memory requirements of the Complex Logarithmic Number System (CLNS) is presented and studied. The chosen algorithm for demonstrating the suitability of LNS for embedded applications is Model Predictive Control (MPC) because of its high computational requirements. Although, there are numerous embedded control problems that could benefit from MPC, it is difficult to incorporate it in real-time systems due to the lack of efficient implementations. Towards this direction a methodology is presented to build an LNS-based hardware coprocessor which relieves a general-purpose microprocessor from the computational burden of MPC, thus enabling the introduction of the algorithm into embedded applications. The reduced-precision LNS unit used makes the system more susceptible to arithmetic anomalies such as catastrophic cancellation and ill-conditioned matrices, which can be detected and mitigated by incorporating Monte Carlo (MC) simulations. The last part of the dissertation explores how the MC method can be used to address these problems and how the performance and accuracy of the MPC implementation are affected.