Gated Clock-based Low-Power Method using RTL Synthesis
Young-Ho Seo, Sung Ho Park, Dongwook Kim · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clockgating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation, clock is gated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. The proposed technique was verified by Power Theater in netleist level after executing synthesis using Design Compiler of Synopsys and 90㎚ CMOS library of TSMC. From result, we identified that the consumed power of register decreased from 922㎻ to 543㎽, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased frm 322mw to 208㎽ (36.5% decrease).