Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation
国武 勇次, Yuji Kunitake, Akihiro Chiyonobu, 千代延 昭宏, Tanaka Koichiro, 田中 康一郎, Toshinori Sato, 寿倫 佐藤 · IEICE Technical Report; IEICE Tech. Rep. · 2006
We have investigated a technique for microprocessors, which achieves both high performance and low power. Based on the observation that critical paths in a circuit are not always active, we aggressively exploit timing violations in the circuit, which do not actually occur. We call the technique Constructive Timing Violation (CTV). Unfortunately, until now, we have evaluated the CTV without considering circuit delay. This paper presents evaluation results of a microprocessor utilizing the CTV, with considering circuit delay in adders. Keyword Performance variations,Circuit delay,Simulations,Typical-case design methodologies