A C-Testable Parallel Multipler Using Differencial Casecode Voltage Swish (DCVS) Logic
Winston A.J. Waller, Syed Mahfuzul Aziz · Kent Academic Repository (University of Kent) · 1994
In this paper, a new C-testable design of a parallel multiplier is presented. It is based on the well known modified Booth's algorithm which reduces the number of partial products by a factor of two compared to the straightforward iterative array multiplier. The multiplier is implemented using the highly testable clocked Differential Cascode Voltage Switch (DCVS) logic. It requires only 21 test vectors to detect all detectable single stuck-at, stuck-on and stuck-open faults. Compared to a non-C-testable DCVS design, it requires only 6 extra inputs, 2 extra outputs and a small amount of extra logic which is also self-checking.