Optimization of H.264 video decoder from Android OS for MIPS32 DSP ASE architectures
Branimir Vasić, Stanislav Očovaj, Darko Lauš, Željko Lukač · 2015
The aim of this study is to present the steps of optimization the H.264/AVC video decoder for MIPS32 DSP ASE SIMD (Single-instruction, multiple-data) processor architecture. In particular, SIMD architecture can be very efficient in the implementation of video applications which have simple operations on 8-bit or 16-bit samples. Besides already mentioned architecture it is also important to get familiar with the H.264/AVC video code standards. The parts of decoder that were subject of optimization were detected as the biggest consumers of CPU resources. After optimization, overall system speedup gain was 36%.