Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang · IEEE Design and Test · 2015
This paper presents the hardware and software architecture of a reusable BIST engine for 3D stacked 14-nm SoC, which also includes software-assisted autorepair of memory defects. Silicon results presented demonstrate the features of such engine such as easy silicon debug, validation time reduction by 3x, detection and repair of memory cell defects, etc. This solution has been successfully designed and used for seven Intel SoCs successfully debugged, tested, and launched into the market place.