Structure of High-Speed Modulo Multiplier Oriented to Repeated Operation
Tadamichi Kudou, Yoshitaka Tsunekawa · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
A high-speed modulo multiplier using redundant representations is presented. It is oriented to repeated operations such as public key cryptosystems which preform repeated modulo multiplications. First, to implement a high-speed modulo multiplier, we show two approaches for radix-2 operations to perform each operations simultaneously. Second, these approaches are applied to radix-4 operations to reduce clock cycles. As a result, the speed of the proposed structure becomes over twice faster than the conventional structures.