Modeling Parallel Computers as Memory Hierarchies (Extended Abstract)
Bowen Alpern, Larry Carter, Jeanne Ferrante · 1993
A generic model that captures the features of diverse computer architectures by approximate parameter choice would facilitate the development of portable programs. A successful generic model must be able to adequately reflect the costs of data movement in real computers. The Parallel Memory Hierarchy (PMH) model of computation uses a single mechanism to model the costs of both interprocessor communication and memory hierarchy traffic. A computer is modelled as a tree of memory modules with processors at the leaves. All data movement takes the form of block transfers between children and their parents. This paper assesses the strengths and weaknesses of the PMH model as a generic model. Such common features as communication cost given in terms of latency and bandwidth, as well as contention on a heavily loaded bus, are easily represented. Specific models for the CM-5, the KSR1, and a 2-dimensional mesh are derived and analyzed.