Multiple-bus, scalable, shared-memory multiprocessors
Michael Carlton, Alvin M. Despain, Randy Howard Katz · 1995
This dissertation presents the design and evaluation of a multiple-bus, cache-coherent, scalable, shared-memory, multiprocessor system, including the architecture, memory consistency model and cache coherency protocol. By coordinating the design of all three components we are able to design a system to optimize performance. The guiding principle was to maximize locality at multiple levels of the system architecture. The cache coherency protocol combines the concepts of shared bus snooping cache schemes and directory-based schemes to scale to large numbers of processors. We also develop a new memory consistency model for multiple-bus based system architectures which reduces hardware support requirements and reduces bus bandwidth usage, leading to more scalable systems. We describe the simulation methodology used to evaluate the performance of the system over a workload of parallel benchmark applications. The research develops principles for effective design of large scale, scalable shared-memory multiprocessors. The simultaneous development of innovative multiprocessor architecture, memory consistency model and cache coherency protocol leads to optimized system performance.