A Vector Graphic Accelerator for Embedded Systems
Yong-Jong Choi, E.-K. Hong, G.-H. Lee, Yongluo Shen, T.-K. Kim, H.-G. Kim, Hyeong-Cheol Oh · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
This paper presents a prototype hardware accelerator for two-dimensional vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process images of 640x240 pixels with moderate complexity at the rate of 30 frames per second. Our current design costs approximately .40 million equivalent gates when it is implemented using a 0.18um CMOS standard cell library.