Scaling issues in multiprocessor memory hierarchies
Jonathan Bertoni · 1992
This dissertation describes two broad areas of research: multiple bus system design and secondary memory systems for high-performance computing. Both areas are components of parallel systems design. The goal of this research is to describe scaling issues in the bus and secondary memory hierarchies, quantifying the performance potential of a variety of schemes proposed in the literature, and some generalizations of those approaches. Both research topics are driven by the same trend: the increase in the performance of processors has outstripped performance gains in other system components. The bus and storage subsystems are both becoming more important to system performance levels as processors spend more and more time waiting for the memory hierarchy. The fundamental goal of this research is to show ways to scale shared-bus multiprocessors, and outline and quantify some limits to such scaling. Some limitations to known methods of bus scaling inherent in DRAM device capabilities and address reference patterns have been quantified, along with some schemes to overcome some of these effects. Various disk organizations likewise have been analyzed and their limitations and utility quantified. The bandwidth requirement for the traces studied was shown to peak at about 6 megabytes per second, providing a tentative target for input-output subsystem performance.