A Diagnosable Design of Programmable Logic Arrays
KK Saluja · 1982
In this paper we propose a multiple fault diagnosable design of PLAs, which uses extra logic (hardware) and some additional controllable inputs and observable outputs. Special attention is paid to the fact that a PLA in a VLSI environment is normally embedded in a larger circuit and its inputs and outputs may not be directly accessible. We make use of Level Sensitive Scan Design (LSSD) of the total circuit to have required access to the inputs/outputs of a PLA. Our design philosophy is compatible with the Built-In Testing (BIT) approach for VLSI circuits. The additional hardware, required to make PLAs diagnosable using our design technique, grows linearly with the size of a PLA (i.e. number of inputs and number of columns in a PLA) and therefore for large size PLAs our design becomes rather attractive to use.