An Integration Technology of Checkpointing for DMR with Energy-Aware
Li Zhong-Wen, Jiang Ye-Peng, Yu Shui · 2022
We present an integrated approach that provides fault tolerance, signature and DVS (Dynamic voltage scaling) for DMR (double modular redundancy). Fault tolerance is achieved through tuning the checkpointing schemes to a given architecture, namely, inserting additional CCPs (compare-checkpoints) or SCPs (store-checkpoints) between CSCPs (store-and-compare-checkpoints). Fault tolerance is then combined with DVS. Introducing the overheads of comparison, storage, DVS, the average execution times to complete a task for proposed schemes are obtained, using renewal equation. In addition, an optimal checkpointing interval that minimizes the average times is analytically derived and is numerically computed. Four schemes are compared as numerical examples and results show that compared to previous approaches, the proposed approach significantly reduces task average execution time. Further, we show how signatures can be used to reduce the overhead of checkpoints in our schemes. Our research results can be applied to the other task duplication systems, such as TMR-F, DMR-F-1 and RFCS, etc..