Wireability of an Ultracomputer
Ronald P. Bianchini · 2011
We analyze the wireability of an Ultracomputer, a shared-memory MIMD parallel machine with thousands of processing elements, wired using an Omega connection network. We show a way of structuring hardware involving large numbers of processors into smaller subsets of processors and switches. A design with 4096 processors, based on present-day wiring technology and electrical power considerations, is presented. This design assumes a 2 x 2 switch on a chip is available, also a 1 megabit memory chip and a high speed microprocessor chip with 32 bit addressing.