An approach to reduce over-testing of path delay faults in data paths using RT-level information
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara · Institutional Repositories DataBase (IRDB) · 2006
In this paper, we present an approach to reduce overtesting of path delay faults (PDFs). To reduce test generation complexity, design-for-testability (DFT) techniques are used in order to make a large number of untestable PDFs in a circuit testable. For a circuit modified by a DFT technique, even if faults corresponding to untestable PDFs in the original circuit are excluded from the fault list targeted by test generation, the faults may still be tested by the generated tests. In our previous work, we proposed a method which identifies a subset of sequentially untestable PDFs for circuits described at register-transfer level (RTL). In this paper, we show that, for a circuit modified by some DFT technique, tests generated by our test generation scheme do not test any fault corresponding to an untestable PDF, which are identified by our method, in the original circuit.