Testing for path delay faults in synchronous digital circuits
Soumitra Bose · 1996
Recent work on path delay testing applies to combinational logic and scan based sequential circuits. Extension to non-scan sequential logic requires that test vectors be applied at variable clock speeds. Such a requirement limits the application of delay testing in practice, where many circuits do not have a combinational test mode and testing must be done at a constant clock rate. We devise new fault simulation and test generation algorithms assuming that all vectors are applied at the rated speed. Multi-valued algebras are a key to many delay test problems. We explore a formal basis for these algebras and present an algorithm to derive optimal algebras for specific test generation problems. The following specific results have been obtained: (1) A new path identification algorithm eliminates the need for explicit path fault dictionaries. This algorithm is used for both test generation and fault simulation. (2) A new algorithm is proposed to obtain a minimal algebra for any test generation problem. This algorithm is shown to formally derive the algebras used in other published and widely known test generation systems for path delay faults. Using this algorithm, a system has been derived for test set compaction by multiple path delay fault activation. (3) Extending the previous research on combinational circuit path delay testing, we formulate the Optimistic Update Theorem, which is a crucial result in the delay test analysis of sequential logic. This theorem determines the flow of fault effects through time frames in a clocked circuit. (4) Finally, we formulate algorithms for test generation for delay faults when all vectors are applied at the rated speed. For the restricted fault size of path delay within two clock periods, a test generator for combinational circuits has been implemented and verified for large combinational ISCAS benchmarks. A symbolic path delay test generator for sequential circuits for the rated speed test methodology has been implemented and results for circuits of moderate size have been obtained.