Design and Demonstration of RSFQ Processor Datapath for High Performance Computing
Alex F. Kirichenko · 2014
Abstract : The main goal of the project is designing in RSFQ technology a 20-GHz 8-bit-wide energy efficient processor datapath consisting of an 8-bit ALU, an 8x8-bit Register File, and an Instruction Decoder. We have had several project modifications resulted in additional tasks, such as the development of energy-efficient zero-static-power dissipation SFQ technology, the development of energy-efficient interface based on a low input voltage polarization modulating VCSELs, and the development of superconducting ferromagnetic Random Access Memory