An Efficient Implemetation of Modular Multiplier for Embedded Systems
Young-Sae Kim, Moo-Seop Kim, Ji-Mann Park, Youngsoo Park · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
In this paper, we present an efficient implementation of Modular Multiplier for embedded systems with performance and area constraints. Basically, The Montgomery algorithm is used and modified considering the very large bit modular multiplication. We combine the algorithm with a new CSA (Carry Save Adder) based architecture. The new architecture is flexible, satisfying various performance and area constraints. It also allows the use of high radices. We have implemented and verified several modular multipliers based on the proposed architecture with FPGA on our ARM7TDMI embedded system emulator. They have been simulated and synthesized in 0.25 ㎛ CMOS technology for VLSI implementation. As a result, it is shown that the architecture contributes to a great flexibility of yielding the best trade-off between hardware cost and throughput rate.