Hardware Implementation of Error Control Decoders
Bainan Chen · OhioLink ETD Center (Ohio Library and Information Network) · 2008
Next, an FPGA implementation of a factorization processor for algebraic soft-decision bit-level generalized minimum distance (BGMD) RS decoding is presented.The BGMD factorization processor utilizes a low-latency and prediction-free scheme for root computation.Furthermore, parallel processing ix architectures and efficient coefficient storage schemes are employed to reduce the latency.Synthesis results show that the BGMD factorization processor for a (255, 239) RS code with maximum multiplicity two can achieve a decoding speed of 815 Mbps on a Xilinx Virtex-II FPGA device.Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory.However, BCH codes often require highly parallel implementations to meet the throughput requirement.As a result, large area is needed.In this thesis, RS codes are proposed to be used for the error correction in MLC flash memory.A (828, 820) RS code has almost the same rate and length in terms of bits as a BCH (8248, 8192) code.Moreover, it has at least the same error-correcting performance in flash memory applications.Nevertheless, with 70% of the area, the RS decoder can achieve a throughput that is 121% higher than the BCH decoder.A novel bit mapping scheme using Gray code is also proposed.Compared to direct bit mapping, the proposed scheme can achieve 0.02 dB and 0.2dB additional gains by using RS and BCH codes, respectively, without any overhead.x