8-Pipeline-Stage 32-bit Embedded Processor Using Dual Clock Domain
Jinook Song, Youngjoo Lee, Bongjin Kim, In‐Cheol Park · 2011
Recently, a fully-integrated embedded system becomes popular for portable device due to the cost reduction and the low-power operation. To reduce the size of the embedded program, some hardware techniques such as nop-before execution and programmable delay slot are introduced in CoreA embedded processor [1], which is 5 pipeline stages with 300MHz at 0.18 um CMOS technology. We develop the second generation of the Core-A which has 8 stages with 500MHz at 90nm CMOS technology. We also develop a cache controller and TLB which support the targeted frequency.