A High Speed and Low Power 4:1 Multiplexer Architecture for Graphic Memory Interface
Ji-Seop Song, Sang-Hyuk Yang, Eung-Ju Kim, Shin-Il Lim, Suki Kim · ICEIC : International Conference on Electronics, Informations and Communications · 2010
This paper proposes the new 4:1 MUX architecture for high speed and low power graphic memory interface. The proposed architecture consists of one 4:2 MUX and one optimized 2:1 MUX. The 4:2 MUX is based on double 2:1 MUX. This proposed 4:1 MUX architecture eliminates the flip-flops in the conventional tree topology and also achieves 33% reduction of power consumption compared to the conventional tree topology, while this new 4:1 MUX shows 2X speed improvement compared to the conventional one stage architecture. The merits of both conventional architectures are simultaneously achieved with this optimized architecture. The simulation results show that 10Gb/s 4:1 MUX in proposed architecture consumes 10㎃ current at 1.8V supply voltage and has over 200㎷ eye opening. All simulations are performed with 0.18㎛ CMOS technology.