A multi-level hierarchical sequential circuit test generation algorithm
Chun‐Hung Chen, Jacob A. Abraham · 1992
The goal of this thesis is to solve the difficult problem of generating high quality tests for large sequential circuits. The approach is to develop a multi-level hierarchical sequential circuit test generation algorithm applicable to a complex design with switch level, gate level, and high level modules. The use of design hierarchy reduces the complexity of test generation since only a limited number of modules need to be considered at any level. The algorithm can be incorporated into a high level test generation system where tests can be generated using structural information for a module in a hierarchical representation of a circuit. In addition, we have incorporated new techniques to improve test generation performance by speeding up the propagation and justification processes when applied to a hierarchical circuit.