Design of a High-Performance Scalable CDMA Router for On-Chip Switched Networks
Daewook Kim, Manho Kim, Gerald E. Sobelman · 대한전자공학회 ISOCC · 2005
Performance results and synthesized area overhead for a code division multiple access (CDMA) router intended for network-on-chip (NoC) applications are presented. Specific architectural block diagrams of the main components of the router are given and synthesis results are provided for 0.18 micron and 0.25 micron structured ASIC libraries. Post-synthesis VHDL simulations verify the functionality of the router and provide values for packet transmission latency and throughput as functions of the payload size. The router can be used to construct star+star and star+mesh network architectures which can be scaled to meet the needs of high-performance applications.