The PCM-1 Cache
IG Mitchell, Ahj Sale · 1989
The PCM-1 processor has an innovative computer architecture for the fast execution of functional programming languages by graph reduction. Expected performance is about 50 Mips (internally) realizing 0.5 million reductions/s. This paper describes the design of the on-chip data cache of the PCM-1 and presents some simulation results on hit-rates in this environment. Little had been known about hit-rates in graph reduction machines and it is shown that surprisingly small caches can be effective in this environment. The cache is organized around systolic array principles, and interfaces between the internal registers, operative unit and the external memory bus. The organization of the cache is believed to be novel. Provision is made for the processor to read and write to the cache; it may also respond to prefetching suggestions and to suggestions to regard a particular memory word as trash.