Efficient persist barriers for multicores
Arpit Joshi, Vijay Nagarajan, Marcelo Silva Cintra, Stratis D. Viglas · 2015
Emerging non-volatile memory technologies enable fast, fine-grained persistence compared to slow block-based devices. In order to ensure consistency of persistent state, dirty cache lines need to be periodically flushed from caches and made persistent in an order specified by the persistency model. A persist barrier is one mechanism for enforcing this ordering.