Delay Optimization using Path Correlation and Gate Sizing
Eunsuk Park, Naeun-Zang, Juho Kim · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
As technology scales into sub-90nm domain, manufacturing varation becomes an increasingly significant portion of circuit delay. Therefore, delays must be modeled as statistical distribution during both analysis and optimization. This thesis applies incremental, parametric statistical static timing analysis(SSTA) to perform gate sizing with a required yield. The proposed algorithm sizes gates which have higher criticality by utilizing probability of critical path while considering path correlation. The result verified an effectiveness of the delay optimization by gate sizing.