Improvement of execution efficiency on a massively parallel SIMD accelerator
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
SIMD (Single Instruction/Multiple Data) type processors have the advantage of smaller area as compared with a general processor, DSP and many MIMD (Multiple Instruction/Multiple Data) type processors. On the other hand, the performance depends on the parallel degree of data in an application. MX Core which was developed by Renesas technology Corp., is a massively parallel SIMD type accelerator. We propose a method to improve execution efficiency of the MX Core in this paper. Our methodology includes optimization of calculation precision and change data transfer structure to MIMD type. As a result of evaluation, we improved parallel operation degree. The proposal structure reduced data transfer pro-cessings of IMDCT by 90%, and speed up processing time of IMDCT by 2.65 times compared with traditional implementation of the MX Core.