Architectural considerations of a wafer scale processor
T. Midwinter, Mary H. Huch, Peter A. Ivey, G. Saucier · 1988
This paper describes some of the work carried out by British Telecom, and partners, as part of the European collaborative project ESPRIT 824. The project is developing a number of wafer scale devices including a single instruction multiple data (SIMD) processor array, with a target performance of 60000 MIPs. The intention is that there will be 128*128 working processing elements on each 4 wafer. Each processing element consists of an ALU, 128 bits of local RAM, an Input/Output register and a control register. This paper considers the design of this high performance SIMD wafer scale processor array. Initially the architectural limitations imposed by wafer scale integration are discussed and a regular array of small processors is shown to be suitable for implementation. The architecture of a single processor is then described, with emphasis being placed on the factors which improve the performance of a SIMD processor. These performance improvements are then integrated into a single design, to show how the ESPRIT 824 processor, ASAP (Advanced Silicon Array Processor), was developed. Finally the paper looks at the performance of a finished ASAP wafer, showing how the 60000 MIPs processing power will be achieved.