Real-time Global Stereo Matching Implementation On FPGA
Sungchan Park, Chao Chen, Hong Jin Jeong · ICEIC : International Conference on Electronics, Informations and Communications · 2008
There are growing needs in stereo vision applications for accuracy, fast calculation, and compact hardware implementation. The global matching techniques based on belief propagation (BP) show robust results with low error rates. However, BP has enormous time and memory complexity that obstruct realization of real-time systems. We present a new parallel architecture with high memory efficiency. The architecture was designed by HDL code and implemented in FPGA chip. With 160 processors that fully operate in parallel, our system is capable of processing video frame with size of 160 480 × at the speed of 15 frames per second. Overall memory usage was reduced 19 times from BP, and average disparity errors were same as BP.