A Power-Aware Scalable Pipelined Multiply-Accumulate Unit with Dadda Reduction Network
Minhyeok Shin, Hanho Lee · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
An energy-efficient power-aware design is highly desirable for digital signal processing (DSP) functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this paper presents a lowpower power-aware scalable pipelined multiply-accumulate (PA-MAC) unit that makes use of dynamic-range detection unit, sharing common functional units, a 16-bit Dadda reduction network with error compensation circuit, a 8-bit Wallace tree and a 4-bit array-based adder-tree for DSP applications.