A SystemC Transaction Level Model for the MIPS R3000 Processor
Y. J. Shin, Sofiène Tahar, Ali Habibi · 2007
Abstract: Processor cores in embedded applications build today the cornerstone of System-on-Chip designs. Among the most successful RISC (Reduced Instruction Set Computer) cores are the MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. In this paper, we design and verify a Transaction Level Modeling (TLM) architecture of the MIPS R3000 in SystemC. The TLM in SystemC is adopted so that abstract data types can be used for higher (abstract) level modeling and faster simulation. The processor is implemented such that the instruction and data caches contain all the necessary instructions and data to eliminate complex memory access management, respectively. To simulate the processor, we provide a script that automatically generates the machine instruction code from assembly language.